Control and filtering¶
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lock¶
Lock A simple lock which computes and applies the feedback to a given parameter using an error signal.
- Syntax
lock name error_signal feedback gain accuracy enabled=true offset=0
- Required
name
: Name of newly created lock.error_signal
: An error signal parameter or an object capable of producing a real-type error signal. This is typically a demodulatedPowerDetector
instance (or the name of the instance).feedback
: A parameter of the model to apply the locks’ feedback signal to.gain
: Control loop gain.accuracy
: Threshold to decide whether the loop is locked.enabled
: If true this lock will run when the RunLocks() action is used. Explicitly specifying the name of the lock will override this setting, e.g. RunLocks(name).offset
: An offset that is applied to the error signal before it is used.
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degree_of_freedom¶
dof
DegreeOfFreedom - Syntax
dof name *node_amplitude_pairs DC=0
- See Also
-
amplifier¶
Amplifier - Syntax
amplifier name gain=1
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filter_zpk¶
zpk
ZPKFilter A zero-pole-gain filter element that is used for shaping signals in simulations. It is a two port element. p1 is the input port and p2 is the output port. Each one has a single node: p1.i and p2.o.
- Syntax
zpk name z p k=none fQ=false gain=1
- Required
name
: Name of element in the modelz
: A 1D-array of zeros. Use [] if none are required. By default these are provided in units of radians/s, not Hz.p
: A 1D-array of poles. Use [] if none are required. By default these are provided in units of radians/s, not Hz.gain
: Overall gain for the filter. Differs from k as this is a Parameter so can be easily switched on/off or varied during a simulation.- Optional
k
: Gain factor for the zeros and poles. If None then its value is automatically set to generate a unity gain at DC.fQ
: When True the zeros and poles can be specified in a tuple of (frequency, quality factor) for each pole and zero. This automatically adds the complex conjugate pair.
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filter_butter¶
butter
ButterFilter - Syntax
butter name order btype frequency gain=1 analog=true
-
filter_cheby1¶
cheby1
Cheby1Filter - Syntax
cheby1 name order rp btype frequency gain=1 analog=true
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test_point¶
test
TestPoint A simple component which has an arbitrary number of test nodes that can be connected to and from.
- Syntax
test name *ports